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AT45DB321C
11. Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
3.0V
0V
1.5V
AC
MEASUREMENT
LEVEL
t R , t F < 2 ns (10% to 90%)
12. Output Test Load
DEVICE
UNDER
TEST
30 pF
13. AC Waveforms
Four different timing waveforms are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK
signal is still low (SCK low time is specified as t WL ). Timing waveforms 1 and 2 conform to Rap-
idS serial interface but for frequencies up to 33 MHz and are compatible with SPI Mode 0 and
SPI Mode 3 respectively. Waveforms 1 and 2 are also compatible with inactive clock polarity low
and inactive clock polarity high, since the maximum specified frequency in that case is 33 MHz.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the t WL period. These timing waveforms are valid over the full frequency range (max-
imum frequency = 40 MHz) of the RapidS serial case.
13.1
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
t CS
CS
t CSS
t W H
t W L
t CSH
SCK
t V
t HO
t DIS
SO
HIGH IMPEDA N CE
V ALID OUT
HIGH IMPEDA N CE
SI
t SU
V ALID I N
t H
23
3387M–DFLASH–2/08
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